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CDB5451A CDB5451A Evaluation Board and Software
Features
Direct Shunt Sensor and Current Transformer Interface for 3-Phase Power On-Board Voltage Reference On-board crystal for XIN Digital Interface to PC Lab Windows/CVITM Evaluation Software
Real-Time RMS calculation Fast Fourier Transform (FFT) Analysis Time Domain Analysis Noise Histogram Analysis
General Description
The CDB5451A is an inexpensive tool designed to evaluate the functionality/performance of the CS5451A 6channel A/D Converter. In addition to this data sheet, the CS5451A Data Sheet is required in conjunction with the CDB5451A Evaluation Board. Six terminal block connectors serve as inputs to the CS5451A's six analog input pairs. The CDB5451A includes an optional voltage reference source for CS5451A. A 4.096MHz crystal is provided as a source for the CS5451A XIN pin, or an external clock source can be supplied by the user. Digital output data from the CS5451A is transferred to the user's IBM-compatible PC via the included 25-pin parallel port cable. The CDB5451A includes PC software, allowing the user to perform data capture (includes option for time domain analysis, histogram analysis, and frequency domain analysis). The software also allows real-time RMS calculation/analysis to be performed simultaneously on all six channels. ORDERING INFORMATION CDB5451A
VAVA+ +5 VIN GND VD+
Evaluation Board
Charge Pump Circuitry
3V Regulator
(Not Populated)
Control Switches
VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2VIN3+ VIN3IIN3+ IIN3-
CPD
VAVA+ GAIN OW RS
RESET FSO SDO CLK SE
Reset Circuit Serial-toParallel Interface Crystal 4.096 MHz
DB25
To PC
CS5451A
XIN V REF IN OUT Header
V REF Voltage Reference
Preliminary Product Information
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This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2001 (All Rights Reserved)
Nov `03 DS458DB3 1
CDB5451A
TABLE OF CONTENTS
1. INTRODUCTION........................................................................................................................ 3 1.1 CS5451A ........................................................................................................................... 3 1.2 Data Flow on Evaluation Board ......................................................................................... 3 2. HARDWARE .............................................................................................................................. 4 2.1 Evaluation Board Description............................................................................................. 4 2.2 Power Supply Connections................................................................................................ 4 2.2.1 Analog Power Supply ............................................................................................... 4 2.2.2 Digital Power Supply ................................................................................................ 4 2.2.3 Charge Pump Options.............................................................................................. 5 2.3 Eval Board Control - Headers/Switches............................................................................. 5 2.3.1 Analog Inputs ........................................................................................................... 7 2.3.2 Voltage Reference Input........................................................................................... 8 2.3.3 Clock Source for XIN................................................................................................ 8 2.3.4 S1 DIP Switch .......................................................................................................... 8 2.3.5 Reset Circuit............................................................................................................. 8 2.3.6 External Signal In/Out Header.................................................................................. 8 2.3.7 Serial-to-Parallel Interface........................................................................................ 8 2.3.8 Connecting the Eval Board to PC............................................................................. 9 3. SOFTWARE............................................................................................................................. 13 3.1 Installing the Software...................................................................................................... 13 3.2 Running the Software ...................................................................................................... 13 3.2.1 Getting Started ....................................................................................................... 13 3.2.2 The Start-Up Window ............................................................................................. 14 3.2.3 The Conversion Window ........................................................................................ 15 3.2.4 Data Collection Window ......................................................................................... 16 3.2.5 Config Window ....................................................................................................... 17 3.2.6 Analyzing Data ....................................................................................................... 18 3.2.7 Time Domain Information ....................................................................................... 18 3.2.8 Frequency Domain Information .............................................................................. 19 3.2.9 Histogram Information ............................................................................................ 20
LIST OF FIGURES
Figure 1. Power Supply, CS5451A, and Oscillator ......................................................... 10 Figure 2. Analog Inputs .................................................................................................. 11 Figure 3. Digital Circuitry ................................................................................................ 12 Figure 4. Start-Up Window ............................................................................................. 14 Figure 5. Conversion Window ........................................................................................ 15 Figure 6. Data Collection Window (Time Domain) ......................................................... 16 Figure 7. Configuration Window ..................................................................................... 18 Figure 8. Data Collection Window (FFT) ........................................................................ 19 Figure 9. Data Collection Window (Histogram) .............................................................. 20 Figure 10.Silkscreen ........................................................................................................ 22 Figure 11.Circuit Side ...................................................................................................... 23 Figure 12.Solder Side ...................................................................................................... 24
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1. INTRODUCTION
The CDB5451A Evaluation Board demonstrates the performance of the CS5451A 6-channel A/D converter. The CDB5451A evaluation board provides a quick means of evaluating the CS5451A. Analysis software supplied with the CDB5451A allows the user to observe the CS5451A's digital output data on the user's PC monitor. The PC software allows the user to quantify the device's performance in the time-domain and frequency domain. The user can save raw data from the CS5451A to a data file, which allows to user to analyze performance with other tools that may be preferable to the user. Additional features of CS5451A include a charge pump driver, on-chip 1.2 V reference, and a digital input that can select between two different output word rates. (The two output word rates are equal to XIN/2048 and XIN/1024.) The CS5451A requires a 1.2 V reference input on VREFIN. The modulators and high rate digital filters allow the user to measure instantaneous voltage and current at an output word rate of 4 kHz (or 2000 kHz, depending on the state of the OWRS pin) when a 4.096 MHz clock source is used.
1.2 Data Flow on Evaluation Board
The output serial bit-stream from the CS5451A is shifted into an 8-bit latch circuit so that it can be quickly ported to the DB25 connector. From this connector, the data can be sent through the provided 25-pin printer cable to the parallel port of the user's IBM-compatible PC (the PC must run under Windows `95/'98/2000 operating system). Once the 8-bit segments of data are ported to the user's PC, the LabWindows software (included with this kit) will re-segment the data into the appropriate 16-bit word format for each of the CS5451A's six data channels. The data is sent quickly to the user's PC, which allows the software to perform various data processing and graphical illustrations on the digital output data. This includes real-time RMS, variance, and standard deviation calculations for all six channels. The output data from each channel can be plotted on-screen in the time domain or in the frequency domain. A histogram function is also included to help the user to evaluate the noise characteristics of each channel. The software can also calculate the mean and standard deviation of the output codes for all six channels. This feature allows the user to scrutinize the variation of the A/D converters if the user applies constant DC voltage levels to the inputs. RMS calculation is also provided to assist in the quick analysis AC input signals.
1.1 CS5451A
The CS5451A is a highly integrated Six-Channel Delta-Sigma Analog-to-Digital Converter (ADC) developed for three-phase power/energy metering applications. However the CS5451A has other potential uses in other data acquisition applications, particularly in motor/servo control applications that require very high precision. The CS5451A combines six delta-sigma modulators with decimation filters, along with a master-mode serial interface on a single-chip device. The CS5451A was designed for the purpose of performing the A/D conversion operations required at the front-end of a digital 3phase metering system. The six ADC channels can be thought of as three pairs of voltage/currentchannel ADC's in a digital 3-phase power metering application. The CS5451A contains one three-channel programmable gain amplifier (PGA) for the three current input channels. The PGA sets the maximum input levels of the all three current channels at 800 mV DC (for gain = 1x) or 40 mV DC (for gain = 20x). The voltage channels have only the 1x gain setting, and so the range of input levels on the voltage channels is 800 mV DC.
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2. HARDWARE 2.1 Evaluation Board Description
The CDB5451A board contains circuitry that will:
2.2 Power Supply Connections
The CDB5451A can be used in several different power supply configurations. Table 1 shows the various possible power connections with the required jumper settings. There are various +3 V and +5 V options. The user must supply the +3V, +5V, GND, and sometimes -2V voltage levels needed to power the evaluation board.
* Accept appropriate DC voltage levels from the user's +3V and/or +5V power supplies, and direct this power to the VA+, VD+, VAand DGND pins of the CS5451A. * Direct the six analog input signals to the six input pairs of the CS5451A. * Supply necessary voltage reference input for the CS5451A's VREFIN pin. * Supply appropriate crystal/oscillator stimulus to the CS5451A's XIN pin. * Direct the output driver signal from the CS5451A's charge-pump driver pin (CPD) which is used produce the negative power supply source for the CS5451A's VA- pin. * Provide a reset switch that allows the user to set the CS5451A's RESET pin from logic "1" to logic "0". * Provide two DIP switches which allow the user to set the logic levels on the CS5451A's GAIN and OWRS input pins. * Detect and receive the data frame signal and digital serial output data signals from the CS5451A's FSO and SDO pins, and send this output data through the included parallel cable, and up to user's PC.
Several areas of blank proto-board space are provided so that, if desired, the user can interface their own electronic sensor equipment onto the board. The output from these sensors can be wired to the six nearby analog input terminal block connectors, which is then fed to the six analog input channels of the CS5451A. Examples of such sensors would include voltage and current transformers, shunt resistors, and resistor divider networks. The next section of this document describes the various sections of the board. After this, operation of the PC software is described in detail.
2.2.1 Analog Power Supply
Referring to Figure 1, the A+ post supplies power to the positive analog power input pin (VA+) of the CS5451A. This post also supplies power to the LT1004 voltage reference (D3) and the optional +3V regulator (U5). If HDR9 is set to the "A-" setting, the A- post can supply the required negative voltage to the VA- pin of the CS5451A. Note that the evaluation board contains the footprints and connectivity which allows the user to install a LM317 voltage regulator (U5), which can be used to create +3 V from a +5 V supply. This option is useful if the user wants to interface the evaluation board to another board that can only operate from a +5V supply. With HDR17 set to "+5V_IN", one single +5 V supply can be used to provide both the +5 V power to a microcontroller and/or other devices, as well as +3 V for the CDB5451A board. The included schematic diagram shows the circuitry for the +5V regulator circuitry inside a box with dashed lines. These components are not populated when the board is shipped from the factory, but the user can install these components if desired.
2.2.2 Digital Power Supply
The A+ post can be used to supply both the analog power (to CS5451A VA+ pin) as well as the digital power (to CS5451A VD+ pin). However if a separate supply voltage is desired for the digital power supply, the "VD+" banana connector post can be used to independently supply a separate digital power supply to the input of the CS5451A (VD+ pin), the 4.096 MHz oscillator (U1), and circuitry for the parallel port interface. This is controlled by the setting on HDR18. The user should note that the CS5451A can operate with a digital supply voltage of either +3V or
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+5V. This voltage is defined as the voltage presented across VD+ and DGND.
2.3 Eval Board Control Headers/Switches
Table 2 lists the various adjustable headers and switches on the CDB5451A Evaluation Board, as well as their default settings (as shipped from the factory). The header settings can be adjusted by the user to select various options on the evaluation board. These options are described further in the following paragraphs.
2.2.3 Charge Pump Options
The output from CS5451A's charge-pump driver pin (CPD) can be used to generate a -2V supply when the proper jumper settings are selected on HDR9. This -2V supply can be used as the negative power supply connection for the CS5451A's VA- pin. Referring to Figure 1, circuitry for a charge-pump circuit is included on-board. The charge pump circuit consists of capacitors C11, C12, and C36, and diodes D1 and D2. As an alternative to using the charge pump circuit, the user can supply an off-board -2V DC power source to the "A-" banana connector. This option is controlled by the setting on HDR9.
2.3.1 Analog Inputs
Refer to Figure 2. The settings on the 12 analog input headers (2 headers per channel) which are designated as HDR1 up to HDR8, and HDR10 up to HDR13, determine which inputs will carry a signal, and which inputs may be grounded. They can be configured to accept either a single-ended or
Power Supplies Analog +3 +3 +3 +3 +3 +3 +3 +3 +3 +3 +5 Digital +3 +3 +3 +3 +3 +3 +5 +5 +5 +5 +3 A+ +3 +3 +3 +3 NC NC +3 +3 NC NC +5
Power Post Connections A-2 -2 NC NC -2 NC -2 NC -2 NC 0 GND 0 0 0 0 0 0 0 0 0 0 +2 D+ +3 NC +3 NC NC NC +5 +5 +5 +5 +5 +5 V_IN NC NC NC NC +5 +5 NC NC +5 +5 NC HDR9
A- O O CPD O O A- O O CPD O O AO CPD O AO CPD O O O O O
HDR17
+5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O O A+ +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O O O O O O O O O O O O O O O O O O O O O O O
HDR18
VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O O O O O O O O O O O O O O O O O O O O O O O
A- O O CPD O O AO CPD O O O
A- O O CPD O O AO CPD O O O
A- O O CPD O O AO CPD O O O
A- O O CPD O O
Table 1. Power Supply Connections
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Name HDR1 Function Description Used to switch IIN3+ on the CS5451A between J2 and AGND. Used to switch VIN3- on the CS5451A between J3 and AGND. Used to switch VIN3+ on the CS5451A between J1 and AGND. Used to switch IIN3- on the CS5451A between J4 and AGND. Used to switch VIN2- on the CS5451A between J6 and AGND. Used to switch IIN2+ on the CS5451A between J7 and AGND. Used to switch IIN2- on the CS5451A between J5 and AGND. Default Setting IIN3+ Set to BNC J2 Default Jumpers
O O O O O O O O O O O O O O O O A- O CPD O O O O O O O
2
O IIN3+ O AGND O VIN3O AGND O VIN3+ O AGND O IIN3O AGND O VIN2O AGND O IIN2+ O AGND O IIN2O AGND O VIN2+ O AGND O O O VIN1+ O AGND O IIN1O AGND O IIN1+ O AGND
3
HDR2 HDR3 HDR4 HDR5
VIN3- Set to BNC J3 VIN3- Set to BNC J1 IIN3- Set to BNC J4 VIN2- Set to BNC J6
HDR6
IIN2+ Set to BNC J7
HDR7 HDR8 HDR9 HDR10 HDR11 HDR12
IIN2+ Set to BNC J5
Used to switch VIN2+ on the CS5451A between J8 VIN2+ Set to BNC J8 and AGND. Used to switch between external VA- and on-board CS5451A charge-pump circuit, CPD CPD active
Used to switch VIN1+ on the CS5451A between J9 VIN1+ Set to BNC J9 and AGND. Used to switch IIN1- on the CS5451A between J12 and AGND. IIN1- Set to BNC J12
Used to switch IIN1+ on the CS5451A between J10 IIN1- Set to BNC J10 and AGND. S1-1 sets logic level on CS5451A OWRS input pin S1-2 sets logic level on CS5451A GAIN input pin
SW1-2 Open (XIN/1024) SW1-1 Open (GAIN=x1)
SW1
OPEN
HDR13
Used to switch VIN1- on the CS5451A between J11 VIN1- Set to BNC J11 and AGND. Used to switch the VREFIN from external VREF post connector, to the on board LT1004 reference, or to the on-chip reference VREFOUT. Refer to Table 3. VREFIN Set to onchip reference VREFOUT
O O
O VIN1O AGND
HDR14
O O O
O LT1004 O VREFOUT O EXT VREF
Table 2. Default Header Settings
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Name HDR15 HDR16 HDR17 Function Description Controls the source for the CS5451A XIN clock input. This header should always be shorted. Determines whether the main analog supply will be powered from the A- post, or from the regulated 3V voltage (generated from the +5V_IN) post input. Choose whether the digital circuitry will be powered by main analog supply, or powered by separate digital supply (through VD+ post). Default Setting Set to on-board 4.000 MHz crystal (U1). Short this header Set to ASet to main analog supply Default Jumpers
O O O O EXT XIN O DGND O 4.0096 MHz OSC O O O O O +5V_IN O A+
HDR18
VD+ O V+ O
O O
Table 2. Default Header Settings (Continued)
differential signal. Using voltage channel #1 as an example (see Figure 2), note that HDR10 sets the input to the positive side of the first voltage channel input (VIN1+ pin). HDR13 sets the input to the negative side of the first voltage channel input (VIN1- pin). In a single-ended input configuration, HDR13 would be set to the "AGND" setting, and HDR10 would be set to "VIN1+" and would conduct the single-ended signal. In a differential input configuration, HDR13 would be set to "VIN1-" and HDR10 would be set to "VIN1+" and this pair of inputs would form the differential input pair into the VIN1+ and VIN1- pins of the CS5451A.
current/voltage transformers and reduced in magnitude before they can be safely applied to the evaluation board. Several patch-circuit areas are provided near the voltage/current input headers, in case the user wants to connect special sensor circuitry to the analog inputs (such as transformers, shunt resistors, etc., for monitoring a 3-phase power line). For each of the three channels, a Shunt Resistor or Current Transformer can be mounted in these areas and connections can be made to the individual current-channel input pairs. Likewise, for each of the three voltage channels, a Voltage Divider or Voltage Transformer can be inserted to drive the CS5451A's three voltage input pairs. Note from Figure 2 that a simple R-C network filters each sensor's output to reduce any noise that might be coupled into the input leads. The 3 dB corner of the filter is approximately 50 kHz differential and common mode. Other header options listed in Table 2 allow the user to set the source of the input clock signal and the source of the voltage reference (VREFIN) input, etc. The voltage reference options and clock input options are discussed next.
WARNING: DANGER! One of the possible applications for the CS5451A includes data acquisition for a power metering system. However, the user should not attempt to directly connect any lead from a high-voltage power line to the evaluation board inputs, even if the current/voltage levels are gain reduced by resistive dividers and/or shunts. Because the ground terminal of the parallel cable (from the PC) is near or at earth ground potential, the ground node on the evaluation board will also be forced to earth ground potential. Serious damage and even personal injury can occur if a "hot" voltage main is connected to any point on the evaluation board, including the analog input connectors. Such power line signals must be isolated by
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2.3.2 Voltage Reference Input
To supply the CS5451A with a suitable 1.2 V voltage reference input at the VREFIN pin, the evaluation board provides three voltage reference options: on-chip, on-board, and external. See HDR14 as shown in Figure 1. Table 3 illustrates the available voltage reference settings for HDR14. With HDR14's jumpers in position "VRE7
CDB5451A
Reference Description Select on board LT1004 Reference LT1004 (5 ppm/C) Select reference supVREFOUT plied from CS5451A VREFOUT pin EXTVREF Select external reference HDR14
O O O O O O O O O O O O O O O O O O
LT1004 VREFOUT EXT VREF LT1004 VREFOUT EXT VREF LT1004 VREFOUT EXT VREF
Table 3. Reference Selection
user to interface the CDB5451A Evaluation Board to other prototype boards, calibrators, logic analyzers, other peripherals, etc. in order to further evaluate the CS5451A device and/or to use the evaluation board as a platform for the prototype development of a digital power meter solution. However, please note that the CDB5451A Evaluation Board is not intended to be integrated directly into a commercial power meter. The layout of the board is not optimized for practical power metering situations.
FOUT," the CS5451A's on-chip reference provides 1.2 volts. With HDR14 set to position "LT1004," the LT1004 provides 1.23 volts (the LT1004 temperature drift is typically 50 ppm/C). By setting HDR14's jumpers to position "EXT VREF," the user can supply an external voltage reference to J16 connector post (VREF) and AGND inputs.
2.3.7 Serial-to-Parallel Interface
Glue-logic on the evaluation board converts the CS5451A serial data into 8-bit segments (bytes). The bytes are sent to the DB25 connector (J17), and then through the standard printer cable to the user's PC. This section briefly describes the operation of the digital circuitry on the CDB5451A that provides the 8-bit parallel data to the PC. Refer to Figure 3. The user should recall from CS5451A Data Sheet that the serial interface on the CS5451A device is a "master-mode" interface, which means that the device provides the clock. Once the CS5451A is powered on, the SCLK pin produces a clock signal, and data is sent out on the SDO pin of the device. When the evaluation software is instructed (by the user) to acquire data through the parallel interface, a two-step process is performed: First the software synchronizes itself to the frame rate of the CS5451A, then the software acquires multiple frames of data from the CS5451A.
2.3.3 Clock Source for XIN
A 4.000 MHz crystal is provided to drive the XIN input of the CS5451A. (See Figure 1.) However, the user has the option to provide an external oscillator signal for XIN, by switching the setting of HDR15.
2.3.4 S1 DIP Switch
Referring to Figure 3, the two single-pole singlethrow switches on SW1 DIP switch should be used to control the logic settings on the CS5451A's OWRS pin and GAIN pin. When these SW1 switches are set to "OPEN" the corresponding pin on CS5451A is set to D+ potential, which creates a logic-high state. When the user closes either of these SW1 switches, the corresponding pin on CS5451A is grounded, which creates a logic-low state on the pin.
2.3.7.1. Synchronization
When the software is commanded to acquire data, the software will first synchronize itself to the frame rate of the CS5451A (see CS5451A Data Sheet). This is done by measuring the amount of time between rising and falling edges of the "BUSY" signal. (BUSY will change state every time the CS5451A issues eight SCLKs--See next section for a more detailed description.) By measuring this time period, the software can determine the idle period of the frame, which allows it to be prepared to collect a complete frame's worth of data when the next CS5451A frame is received. This acquisition sequence is described next.
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2.3.5 Reset Circuit
Circuitry has been provided which allows the user to execute a hardware reset on the CS5451A. (See Figure 3). By pressing on the S1 switch, the RESET pin on the CS5451A will be held low until the switch is released.
2.3.6 External Signal In/Out Header
Note that HDR16 is included on the CDB5451A Evaluation Board as a header that is normally left unconnected. This header provides a way for the
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2.3.7.2. Acquisition
Referring to Figure 3, the CS5451A's SCLK line is used to clock the 8-bit serial-in/parallel-out shiftregister (U7) which accepts the serial data on SDO and shifts it into the 8 output bits QA-QG. The SCLK signal is also fed into the up/down counter U6 and after every 8 SCLKs, the "QC" pin of U6 will latch the QA-QG output bits of U6 into the 8-bit DFlip-Flop (U3). While this is happening, the software monitors the "BUSY" signal (from the "QD" pin of U6). BUSY is the critical handshake signal. A rising or falling transition on BUSY indicates to the software that it is now time to collect another byte of data from the latched output on U3. After sixteen SCLKs, the PC software has acquired two bytes (16 bits) which represents one data sample. The 4-bit up/down counter (U6) will roll over after every 16 SCLKs. (Note that U6 is cleared by the CS5451A's FSO signal at the beginning of each frame, which insures that the counter begins the frame in the correct state--cleared). This sequence, which lasts for 16 SCLKs, is performed a total of six times in order to obtain the six 16-bit words from the CS5451A. After the last 16-bit word is acquired, the software recognizes that the end of a data frame has been reached, and it will continue to wait for the next transition on the "BUSY" line. This will not occur until the first 8 SCLKs of the next frame are sent from the CS5451A. Various other signals in Figure 3 (STRB, FEED, ACK, etc.) are not used during data capture and are only used for testing (internal use only).
2.3.8 Connecting the Eval Board to PC
The CDB5451A connects to the user's IBM-compatible PC with the included 25-pin parallel port cable. The user should not connect this cable between the CDB5451A and the parallel port on the PC until all of the header options in Table 2 have been set to appropriate settings and the user has applied power to the CDB5451A. The parallel cable attached to the CDB5451A Evaluation Board at J17. After connecting the parallel port cable between the PC and CDB5451A, the user should always actuate (press down on) the "RESET" switch (S1) at least one time before performing any other evaluation activities.
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100
Z4 P6KE6V8P . 1UF R31 R29 . 1UF 22UF
C42
1
C39
C40
C41
10UF
1K
GND
140
R30
CON_BANANA
HDR17 HDR2X2
4. 7UF TANT
GND
GND
3
VI N3I N3+ I N3I I N2I I N2+ VI N2-
BNC_RA
D3 LT1004
C19 C16
VAVI N3+ VI N2+ I I N1-
J 13
GND
2
4
1
3
HDR2X2 HDR9
10
+5V
U5 LM 317LZ
3
CON_BANANA
TP40 TP77
3. 0V
2
+5V_I N
IN ADJ
OUT
J 21
C38 U4 . 33UF TANT
SCLK SDO FSO SE / GAI N AGND VREFI N VREFOUT VA+ VAVI N3+ VI N3I N3+ I I N2+ I I N2I N3VI N2VI N2+ I I N1I I N1+ VI N1VI N1+ OW RS / RESET XI N CPD DGND VD+
GND
HDR18 HDR2X2
1 3 4 2
D+
HDR1X2 HDR16 1 2
V+
CON_BANANA
Do Not Popul at e
C21 10UF . 1UF C14
SCLK SDO FSO SE / GAI N
VD+
CON_BANANA
C22 . 1UF
C23 47UF
Z3 J 20 P6KE6V8P
GND
GND
J 18
GND
C20
GND
. 1UF
VI N3+ VI N3I N3+ I N3-
TP36 TP38 TP40 TP42 TP44 TP46 TP48 TP50 TP52 TP54 TP56 TP58 TP60 TP62
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
TP37 TP39 TP41 TP43 TP45 TP47 TP49 TP51 TP53 TP55 TP57 TP59 TP61 TP63
XI N / RESET OW RS VI N1+ VI N1I I N1+ I I N1VI N2+ VI N2I I N2+ I I N2-
TP79 TP73 TP74 TP14 TP17 TP19 TP21 TP23 TP25 TP27 TP29 TP31 TP33 TP35
TP78 TP72 TP75 TP15 TP16 TP18 TP20 TP22 TP24 TP26 TP28 TP30 TP32 TP34
GND
+3V
GND
C37
SSOP28_200_P65M M
V+
L1 U2
SCLK VD+ DGND CPD XI N / RESET OW RS VI N1+ VI N1I I N1+ SDO FSO SE / GAI N AGND VREFI N VREFOUT VA+
A+
1 2
3
4
R2
10 FERRI TE_BEAD
J 14
Z2 C13 47UF . 1UF
HDR3X2 HDR14
2 1 3 5 4 6
C17 R3 4. 99K TP40 TP1 TP40 TP76
2
P6KE6V8P
SCLK SDO FSO SE / GAI N
1. 2V +3V
. 1UF . 1UF SKT_SSOP28_ENP
VI N3+ VI N3I N3+ I N3-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND EXT_I N
XI N / RESET OW RS VI N1+ VI N1I I N1+ I I N1VI N2+ VI N2I I N2+ I I N2-
CON_BANANA
GND GND GND
4. 0960M HZ
GND
HDR3X2 HDR15
EXT VREF
C18
D+
7
GND R32 10 . 1UF
14 8
2 4 6
1 3 5
J 16
TP2 TP40 TANT 4. 7UF C36 C2 . 1UF C11 D2 BAT85
GND
XI N
VCC U1
GND
CON_BANANA
A-
J 15
. 039UF D1 BAT85
Z1 P6KE6V8P C15 47UF C1 . 1UF
TANT 2. 2UF C12
GND GND
CDB5451A
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Figure 1. Power Supply, CS5451A, and Oscillator
J 22
1 2 3 4
1 2 3 4
GND GND
J 25
J 23
1 2 3 4
GND
GND
1 2 3 4
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TP67
HDR2X2 HDR7
1 3 4 2
J5
R23
I I N2-
BNC_RA
301 0. 1% C24 . 01UF C8
GND
4700PF TP66
HDR2X2 HDR6
J7
GND I I N2+
R22
1 3 4 2
BNC_RA
301 0. 1% C25 . 01UF
GND
TP65
HDR2X2 HDR5
J6
GND VI N2-
R21
1 3 4 2
BNC_RA
301 0. 1% C26 . 01UF C7
GND
4700PF TP64
HDR2X2 HDR8
J8
GND VI N2+
R24
1 3 4 2
BNC_RA
301 0. 1% C27 . 01UF
GND
J 24
1 2 3 4
1 2 3 4
TP4
HDR2X2 HDR11 J1
1 3 4 2
TP71 R19
I I N1BNC_RA
HDR2X2 HDR3
1 3 2 4
J 12
R26 C28 . 01UF
BNC_RA
301 0. 1% C9
GND
301 0. 1% C6 4700PF TP70
GND
VI N3+
C32 . 01UF
4700PF TP5
HDR2X2 HDR12
J 10
GND I I N1+
J3 BNC_RA
HDR2X2 HDR2
GND
R27
1 3 4 2
R18
1 3
2 4
BNC_RA
301 0. 1% C29 . 01UF
GND
301 0. 1%
GND
VI N3-
C33 . 01UF TP69
TP6
HDR2X2 HDR13
J 11
GND VI N1-
J2 BNC_RA
HDR2X2 HDR1
GND
R28
1 3 4 2
R17
1 3
2 4
BNC_RA
301 0. 1% C30 . 01UF C10
GND
301 0. 1% C5 4700PF TP68
GND
I N3+
C34 . 01UF
4700PF TP3
HDR2X2 HDR10
1 3 4 2
J9
R25
GND VI N1+
J4 BNC_RA
HDR2X2 HDR4
GND
R20 C31 . 01UF
1 3
2 4
BNC_RA
301 0. 1%
GND
301 0. 1%
GND
I N3-
C35 . 01UF
J 26
GND
J 27
GND
CDB5451A
Figure 2. Analog Inputs
11
OW RS / RESET / GAI N SE FSO SCLK SDO
QD DATA C 8
HDR7X2 HDR19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 QC LOAD 10 9 11 7 GND DATA D
M 74HC193N M
GND BUSY I NI T
GND
U8
GND
19
2/ G R9 470
SE ACK
R15 4. 7K 470 C45 SN74HC240N 220PF COG
11 13 15 17
R7
D+
2A1 2A2 2A3 2A4
2Y1 2Y2 2Y3 2Y4
9 7 5 3
10K
10K
R6
10K
OPEN
/ GAI N OW RS
SW P_2 _DI
R35 R34
2 1
10K 10K SN74HC164N
GND GND
R33
R16
10K
10K
U8 R4 R11 R5
20
GND
VCC 470
18 16 14 12 10
1/ G 1Y1 1Y2 1Y3 1Y4 GND SN74HC240N
GND
1
SCLK
1A1 1A2 1A3 1A4
2 4 6 8
R12 R14
4. 7K 4. 7K
CDB5451A
DS458DB3
Figure 3. Digital Circuitry
R1
D+ STRB FEED
10K
12
C43
D+
. 1UF
GND
D+
U6
1 DATA B QB QA CD CU CARRY 12 BORROW 13 CLR 14 DATA A 15 VCC 16 2 3
R8 470
FSO
4 5
D+
DB25M _RA J 17
GND
SW 1
GND
SN74HC374N GND
7
. 1UF C4 GND VCC
10 20
D+
/ RESET
D+
R36
20K 49. 9
SDO
R10 470
2 1 8 9
QG QF QE QD QC QB QA B A CLK / CLR U7
GND
13 12 11 10 6 5 4 3
18 17 14 13 8 7 4 3
8D 7D 6D 5D 4D 3D 2D 1D VCC
14 11 1
8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q CLK / OC U3 C3 . 1UF
D+
19 16 15 12 9 6 5 2
R37
GND
C46 S1 SW _B3W _1100
GND
. 1UF
R13
4. 7K
SEL D+ GND D+
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
. 1UF
C44
CDB5451A
3. SOFTWARE
The evaluation software was developed with Lab Windows/CVITM, a software development package from National Instruments. The software is designed to run under Windows 95TM or later, and requires about 3 MB of hard drive space (2 MB for the CVI Run-Time EngineTM, and 1 MB for the evaluation software). Before installing the software, read the readme.txt file for any last minute updates or changes. More sophisticated analysis software can be developed by purchasing the development package from National Instruments (512-7940100).
chosen to accommodate a variety of computers).
3.2 Running the Software 3.2.1 Getting Started
The CDB5451A Evaluation software allows the user to obtain, display, and save data that is acquired by the CS5451A chip. Before running the software, the first step is to make sure that all of the headers that are listed in Table 2 are set to an appropriate setting, the exact setting should be determined by the user. Next, with the user's DC power supplies still turned off, the user should connect the necessary power leads to the banana jack power connectors on the evaluation board. Refer to Table 1 for various acceptable power supply connection configurations. Then at this time the user should turn on their DC power supplies, which should apply power to the CDB5451A. Several test point locations are available on the evaluation board. The user can check these test points with a voltmeter, to make sure that the voltages at these test points are at the expected levels. When the user has verified that the power supply levels are constant, the user should connect the included 25pin cable between J17 of the evaluation board and the parallel port on the user's PC. The user should then press down on the S1 "RESET" switch, and make sure to hold it down for at least ~0.5 seconds before releasing. Finally, the user can start the PC software. To start the software, double click on the EVAL5451A icon, or initiate through the Start menu.
3.1 Installing the Software
Installation Procedure: 1) Turn on the PC, running Windows 95TM or later. 2) Insert the Installation CD into the PC. 3) Run the appropriate installer package (either instmsi.exe or instmsiw.exe, depending on the operating system). See the readme.txt file for more information. 4) Run EVL5451A.msi to begin installation. 5) During installation the user will be prompted to enter the directory in which to install the LabWindows CVI Run-Time EngineTM. The RunTime EngineTM manages executables created with Lab Windows/CVITM. If the default directory is acceptable, select OK and the Run-Time EngineTM will be installed there. 6) After the Run-Time EngineTM is installed, the user is prompted to enter the directory in which to install the CDB5451A software. Select OK to accept the default directory. 7) Once the program is installed, it can be run by double clicking on the EVL5451A icon, or through the Start menu.
Note: The software is written to run with 640 x 480 resolution; however, it will work with 1024 x 768 resolution. If the user interface seems to be a little small, the user might consider setting the display settings to 640 x 480. (640x480 was
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CDB5451A
Figure 4. Start-Up Window
3.2.2 The Start-Up Window
When the software first executes, the user should see the Start-Up Window appear on the user's PC monitor. This window is shown in Figure 4. From this window, the user can navigate to three other main windows: the Conversion Window, the Data Collection Window, and CS5451A Pinout Diagram. (The CS5471 Pinout Diagram is included in a fourth window. Cirrus Logic's CS5471 device is very similar to CS5451A, except this device has only the first pair of voltage/current input channels.) To navigate to these windows, use the mouse to click on the "Menu" item, which is located towards the upper left corner of the Start-Up Window. "Menu" is a pull-down menu which contains
four options. From this pull-down menu, the user can select any of the three windows mentioned above, and once this is done, the new window should appear. A fourth option called "Exit" should be selected when the user wants to terminate execution of the evaluation board software program. If the user selects the "CS5451A Pinout Diagram" option in the "Menu" pull-down, the software will display a window which contains the pin diagram of the CS5451A. This pin diagram is included for the user's reference. Note that this window has no actual functionality. The functionality of the Conversion Window and the Data Collection Window is described next.
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CDB5451A
3.2.3 The Conversion Window
Refer to Figure 5. After the user presses on the green-colored "START" button in this window, the software will begin to collect data for all six channels of the CS5451A. For each of the six channels, a certain number of continuous instantaneous data samples are bundled together. The period over which each bundle of samples is taken is called a "computation cycle." The user controls the number of instantaneous data samples that will be taken (per channel) during one computation cycle by adjusting the number in the box labeled "Evaluation Software Cycle Count." Note that the default value for this is set to 4000. Thus during every computation cycle, the PC software will acquire 4000 samples (from each of the six channels) and it will update the on-screen results of all six channels after calculating the results on each successive set of 4000 samples. The results that are displayed on this screen are therefore updated after each computation cycle. Note that the results of the very first computation cycle (after the "START" button has been activated) will not be valid. Accuracy of the Mean/Std. Dev/RMS results increases as the "Evaluation Software Cycle Count:" value is increased. The user should understand how to interpret the values that are displayed in the 4x6 array of number boxes in the Conversion Window. The result values displayed in these 24 numeric output boxes are expressed on a normalized scale. The highest value (0.999...) represents the highest digital output code that can be issued from the CS5451A (which is +32767), while the lowest value -0.999... represents the lowest output code that can be issued from the CS5451A (which is -32768). This is because the CS5451A issues instantaneous output codes as two's complement 16-bit words. Therefore, the range of values that can be returned from the CS5451A are between -32768 and +32767. The CS5451A issues instantaneous data, and every computation cycle, the software computes/displays the quantities which are described below:
Figure 5. Conversion Window
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CDB5451A
Figure 6. Data Collection Window (Time Domain)
3.2.3.1. Last Value
The first column is labelled as "Last Value." The value in this box represents the value of the very last instantaneous sample that was taken (for each channel) in the most recently-completed computation cycle. If the user's analog input waveforms are AC in nature, then this column of results will rarely have any meaning. But if the user applies a constant DC input signal to any of the analog input channels, then the Last Value column for that channel should display an output code that is relatively constant from one conversion cycle to the next.
3.2.3.3. Std Dev.
The values in this column represent the computed standard deviation over the set of values in the most recent computation cycle.
3.2.3.4. RMS
The values in this column represent the computed RMS value over the most recently-completed computation cycle.
3.2.4 Data Collection Window
The Data Collection Window (Figs 6, 8, and 9) allows the user to collect samples sets of data from CS5451A and analyze them using time domain, FFT, and histogram plots. The Data Collection Window is accessible through the Menu option, or by pressing F4.
3.2.3.2. Mean
The values in this column represent the simple average of the sample values in the latest computation cycle.
3.2.4.1. Collect Button
This button will collect data from the CS5451A, to be analyzed in the plot area. See the section on Collecting Data Sets for more information.
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3.2.4.2. Time Domain / FFT / Histogram Selector
This selector button is located just to the right of the Collect Button. The label on this button will change as the user selects which analysis is to be performed ("Time Domain" or "FFT" or "Histogram"). When the software is first started, the default mode on this selector button is Time Domain. This user should click on this button to select which type of data processing to perform on the collected data and display in the plot area. Refer to the section on Analyzing Data for more information. located just to the left of the SAVE button. The data collected for all six channels will be saved to a text file.
3.2.4.7. Load Button
The green colored LOAD button will load any data file that was previously generated by clicking on the red SAVE button. The exact path and filename must be specified by the user in the text window located just to the left of the LOAD button.
3.2.4.8. Channel Selector Buttons
Clicking on six buttons labeled as "V1" "V2" "V3" and "I1" "I2" "I3" will display a certain channel of data. "V1" refers to the data taken from the Vin1+/Vin1- input pins of the CS5451A. This is similar for "V2" and "V3". In a similar manner, clicking on the "I1" "I2" "I3" buttons will display the voltage measured across the first, second, and third pairs of current channel input pins (designated as IinA+/IinA- for A = 1, 2, 3).
3.2.4.3. "Crystal" Value Indicator Box
The value in this box reflects the frequency of the CS5451A's clock input (at the XIN pin). Since the XIN frequency affects the sampling rate (the output word rate) of the CS5451A, this information must be specified to the software so that it can accurately depict the frequency-content of the sampled data (in Hz) when performing an FFT analysis. The user can enter the crystal frequency that is used on the CDB5451A board into this box. The default value of this box is set for the on-board 4.096MHz oscillator.
3.2.5 Config Window
See Figure 7. Clicking on the Config button will bring up a small pop-up window called the Config Window. The Config Window allows the user to set up the data collection and analysis parameters, which are described next.
3.2.4.4. OWRS Pin Setting:
This switch should be adjusted whenever the user toggles the S1-1 DIP switch (on the evaluation board). The default setting of this switch is HI, corresponding to the default setting on S1-1 (default setting is "OPEN"). S1-1 drives the CS5451A's OWRS pin to logic "1". A logic "1" on OWRS sets the sampling frequency of all six CS5451A input channels to XIN/1024. To toggle the state of the on-screen switch, simply click on the switch with the mouse.
3.2.5.1. Number of Samples
This box allows the user to select the number of samples to collect. The user can choose any whole-number power of 2 between 16 and 32768.
3.2.5.2. Average
When performing FFT processing, this box will determine the number of FFTs to average. FFTs will then be collected and averaged when the user clicks on the Collect Button.
3.2.4.5. Config Button
This button will bring up the configuration window (shown in Fig 7) in which the user can modify the data collection specifications. See the discussion of the Config Window in this document.
3.2.5.3. FFT Window
This box allows the user to select the type of windowing algorithm for FFT processing. Windowing algorithms include the Blackman, Black-Harris, Hanning, 5-term Hodie, and 7-term Hodie. The 5term Hodie and 7-term Hodie are windowing algorithms developed at Cirrus Logic.
3.2.4.6. Save Button
The red-colored SAVE button will save the data in the current plot to a file. The exact path and filename can be specified by the user in the text window
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CDB5451A
3.2.5.7. Crystal (MHz)
This frequency value is used to properly perform the FFT operation on a set of collected data. The user can adjust this value. Default value is 4.096 (Mhz), which is the frequency of the crystal oscillator (U1) on the evaluation board.
3.2.6 Analyzing Data
The evaluation software provides three types of analysis tests - Time Domain, Frequency Domain, and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of Output Code versus Conversion Sample Number. The Frequency Domain analysis processes acquired conversions to produce a magnitude versus frequency plot using the Fast-Fourier transform (results up to Fs/2 are calculated and displayed). The Histogram analysis test processes acquired conversions to produce a histogram plot. Statistical noise calculated are also calculated and displayed.
Figure 7. Configuration Window
3.2.5.4. Histogram Bin Width
This box allows for a variable "bin width" when plotting histograms of the collected data. Each vertical bar in the histogram plot will contain the number of output codes contained in this box. Increasing this number may allow the user to view histograms with larger input ranges.
3.2.7 Time Domain Information
The following controls and indicators are associated with the Time Domain Analysis. Time domain data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to "Time Domain."
3.2.5.5. Samples to Discard
This number represents the number of CS5451A sample periods that will be ignored before the software starts to collect samples (when the user presses on the Collect Button). After the software has skipped over this many data samples, the software will then begin to save samples from the device (for all six channels). The number of samples that are actually saved is equal to the number specified in the Number of Samples box.
3.2.7.1. Count
Displays current x-position of the cursor on the time domain display.
3.2.7.2. Magnitude
Displays current y-value of the cursor on the time domain display.
3.2.7.3. Maximum
Indicator for the maximum value of the collected data set.
3.2.5.6. Ready Button
After the user has adjusted the parameters in the Config Window to the desired settings, the user must click on the READY button to close the Config Window and return to the Data Collection Window.
3.2.7.4. Minimum
Indicator for the minimum value of the collected data set.
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3.2.8 Frequency Domain Information
The following section describes the indicators associated with Fast Fourier Transform (FFT) analysis. FFT data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector button to "FFT."
3.2.9.2. Magnitude
Indicator for the maximum value of the collected data set.
3.2.9.3. Mean
Average value of the collected data set.
3.2.8.1. Frequency
Displays the x-axis value of the cursor on the FFT display.
3.2.9.4. Variance
Indicator for the calculated variance of the collected data set.
3.2.8.2. Magnitude
Displays the y-axis value of the cursor on the FFT display.
3.2.9.5. STD_DEV
Indicator for the calculated standard deviation of the collected data set.
3.2.8.3. S/D
Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels).
3.2.9.6. Maximum
Indicator for the maximum value of the collected data set.
3.2.8.4. SINAD
Indicator for the Signal-to-Noise + Distortion Ratio (decibels).
3.2.9.7. Minimum
Indicator for the minimum value collected in the data set.
3.2.8.5. SNR
Indicator for the Signal-to-Noise Ratio, first 4 harmonics are note included (decibels).
3.2.8.6. S/PN
Indicator for the Signal-to-Peak Noise Ratio (decibels).
3.2.8.7. FS-PdB
Not using windowing, how far down from zero the peak voltage input value is (decibels).
3.2.9 Histogram Information
The following is a description of the indicators associated with Histogram Analysis. Histogram can plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to "Histogram."
3.2.9.1. Bin
Displays the x-axis value of the cursor on the Histogram.
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Figure 8. Silkscreen
20
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Figure 9. Circuit Side
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CDB5451A
Figure 10. Solder Side
22
DS458DB3
CDB5451A
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CDB5451A
C ontacting C irrus Logic Support
For all product questions and inquiries contact a C irrus Logic Sales R epresentative. T o find the one nearest to you go to w w w .cirrus.com
IM PO RTA NT N O TICE "Prelim inary" product inform ation describes products that are in production, but for which full characterization data is not yet av ailable. Cirrus Logic, Inc. and its subsidiaries ("C irrus") believe that the inform ation contained in this docum ent is accurate and reliable. However, the inform ation is subject to change without notice and is provided "A S IS" without warranty of any kind (express or im plied). Custom ers are advised to obtain the latest version of relevant inform ation to verify, before placing orders, that inform ation being relied on is current and com plete. A ll products are sold subject to the term s and conditions of sale supplied at the tim e of order acknowledgm ent, including those pertaining to wa rranty, patent infringem ent, and lim itation of liability. No responsibility is assum ed by Cirrus for the use of this inform ation, including use of this inform ation as the basis for m anufacture or sale of any item s, or for infringem ent of patents or other rights of third parties. This docum ent is the property of Cirrus and by furnishing this inform ation, Cirrus grants no license, express or im plied under any patents, m ask work rights, copyrights, tradem arks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the inform ation contained herein and gives consent for copies to be m ade of the inform ation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or prom otional purposes, or for creating any work for resale. CE RTA IN A PP LICA TIO NS U SING SEM ICO ND UCTO R P RO D UCTS M AY INVO LVE PO TEN TIAL RIS KS O F DE ATH , PE RS O NAL IN JUR Y, O R SEVER E PR O PE RTY O R ENVIRO NM E NTA L DAM A GE ("CRITICA L A PPLICATIONS "). CIRR US PR O D UCTS A RE N O T D ESIG NE D, A UTHO RIZED O R W AR RAN TED FO R USE IN AIRC RAFT SY STEM S, M ILITARY AP PLICATIO NS, PR O D UCTS S URG ICALLY IM PLA NTE D INTO THE BO D Y, LIFE S UP PO RT PR O D UCTS O R O TH ER CR ITICAL APP LICA TIO NS (INCLUDIN G M EDICAL DEV ICES , AIRCR AFT SYS TEM S O R CO M PO NE NTS A ND PE RSO N AL O R AU TO M O TIVE SAFETY O R SEC URITY DE VIC ES). INC LUS IO N O F CIRRU S P RO DUC TS IN SU CH APP LICATIO N S IS UN DER STO O D TO BE FULLY AT THE CU STOM E R'S RISK AND CIR RUS DIS CLAIM S AND M AK ES NO W ARR ANTY, EXPRE SS , STATU TO R Y O R IM P LIED , IN CLU DING TH E IM P LIE D W ARRA NTIE S O F M E RCH AN TABILITY AN D FITNE SS FO R PA RTICULAR P UR POS E, W ITH REG ARD TO ANY CIRRU S PRO DU CT THAT IS U SE D IN SUC H A M AN NER . IF THE CU STO M E R O R CU STO M E R'S CUSTO M E R U SES O R PERM ITS TH E US E O F CIRRU S P RO DU CTS IN CRITICA L AP PLICATIO NS, C USTOM E R AG REE S, B Y SU CH USE, TO FULLY INDEM NIFY CIRRU S, ITS O FFICER S, DIREC TO RS , EM PLO YE ES, DIS TRIB UTO RS A ND O TH ER A G E NTS FROM A NY A ND A LL LIABILITY, INC LUD ING ATTO RN EYS ' FE ES AND CO STS , THAT M AY RE SULT FRO M O R A RISE IN C O N NEC TIO N W ITH TH ESE US ES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are tradem arks of C irrus Logic, Inc. All other brand and product nam es in this docum ent m ay be tradem arks or service m arks of their respective owners. IBM is a tradem ark of International Business M achines C orporation. W indows is a tradem ark of M icrosoft C orporation. Lab W indows and C VI are tradem arks of N ational Instrum ents. SP I is a tradem ark of M otorola, Inc. M icrowire is a tradem ark of N ational Sem iconductor.
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